# EE6301 Digital Logic Circuits Question Bank

## Sample EE6301 Digital Logic Circuits Question Bank:

Part A 2 mark

1. Define combinational logic.

2. Explain the design procedure for combinational circuits.

3. Define Boolean algebra & Boolean Expression.

4. What are basic properties of Boolean algebra?

5. State the associative property of Boolean algebra.

6. State the commutative property of Boolean algebra.

7. State the distributive property of Boolean algebra.

8. State De Morgan’s theorem. (EE6301 Digital Logic Circuits Question Bank)

10. What are the 2 forms of Boolean expression?

11. Define Minterm & Maxterm.

12. What is meant by karnaugh map or K-Map method?

13. Define Cell.

14. Define Pair, Quad, and Octet.

15. What are called don’t care conditions?

16. What is tabulation method? (EE6301 Digital Logic Circuits Question Bank)

17. State the limitations of karnaugh map.

18. What is a prime implicant?

19. What is an essential prime implicant?

20. Explain or list out the advantages and disadvantages of K-map method?

22. Define Duality Theorem. (EE6301 Digital Logic Circuits Question Bank)

24. Define multiplexer?

25. What is Demultiplexer?

26. What is code conversion?

27. What is code converter?

28. What do you mean by analyzing a combinational circuit?

29. Give the applications of Demultiplexer.

30. Mention the uses of Demultiplexer. (EE6301 Digital Logic Circuits Question Bank)

31. Give other name for Multiplexer and Demultiplexer.

32. What is the function of the enable input in a Multiplexer?

33.List the application of Mux.

34.List out the applications of comparators?

35. What is digital comparator?

36. What is carry look-ahead addition? (EE6301 Digital Logic Circuits Question Bank)

Part B – 16 mark

1.Obtain the minimum SOP using using K-map.
F=m0+m2+m4+m8+m9+m10+m11+m12+m13

2.determine the prime applicants of the following function and verify using K- Map F(A,B,C,D)=m(3,4,5,7,9,13,14,15).

3.Using 8:1 multiplexer, realize the Boolean function
T=f(w,x,y,z)=m(0,1,2,4,5,7,8,9,12,13)

4.Design and implement the full adder and full subtractor circuit.

5.Design and implement a 8421 to gray code converter. Realise the converter using only NAND gates.

6.Obtain the minimum SOP using K-map method f(a,b,c,d)=m(1,3,4,6,11) +d(0,8,10,12,13). (EE6301 Digital Logic Circuits Question Bank)

 Subject Name Digital Logic Circuits Subject code EE6301 Regulation 2013

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